EMC Design Guidelines for PCB Designs

These Electromagnetic Compatibility (EMC) design guidelines are here to help you to understand the basics on how to make a good EMC PCB design or EMC cabling design.

Following these guidelines helped many engineers to succeed in EMC testing of several products. However, be aware that guidelines alone cannot do magical things to your design.

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Preface to the Guidelines:

I am trying to avoid the terms ground plane and GND plane in our guidelines. Whenever appropriate, we use the terms signal return plane or return signal reference plane or simply: reference plane.

Why this?

Currents flow in loops. A current does always return to its source. And a common issue is that engineers tend to forget about this when they design PCBs and electronics systems, especially when they design digital systems where you can only see the signal traces from chip to chip and the return current flows through the "GND symbols" in the schematic.

The majority of EMC problems (e.g. radiated emission, ESD) involve high-frequency signals (several megahertz - MHz).

It is important to understand that a return current of a signal above about 50 kHz takes the path of lowest impedance and prefers to flow close to the forward current, e.g. directly under the forward current in an adjusted power supply or ground plane - the so called return signal reference plane.

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PCB DESIGN

EMC Guidelines #1:

Never route signals over split reference planes...

Lower radiated emission

Do not route signals over split return signal reference planes (GND, power planes)

Never!

This leads to unnecessary large current loops (as the current return cannot flow directly under/beside the forward current) and large current loops in general lead to high radiated emission values.

Rule Of Thumb #1:

Do not split return current reference planes (GND, power planes), go with a solid filled reference plane instead.

There must be a good reasons for splitting planes.

There should always be at least one solid reference plane closely adjusted to signals.

EMC Guideline #2 –

Keep current loops as small as possible...

Lower radiated emission

Always consider the return current! Always! And with the return current in mind: minimize the loop you have between forward and return current. This is especially true for high-frequency signals (several MHz), in other words: clocks! As Dr. Henry W. Ott said: “Get paranoid about clocks!”.

This is a very generic guideline and should always be kept in mind.

Out of this guideline, many others will follow here in a more specific way.

​Note #1:

I assume that you have a high-frequency signal (S1,> 50kHz) trace on layer 1 and a reference plane (e.g. GND or power plane) on the neighbor layer 2, the return current of the high-frequency signal (S1) on the reference plane prefers to flow directly under the trace of S1.

Read more details in this book here or the preface of these guidelines.

EMC Guideline #3 –

Decoupling: use low-inductance capacitors / traces & planes..

Lower radiated emission, lower impedance coupling

Decoupling is important! Always consider decoupling! Place ceramic capacitors close to EVERY power supply pin of EVERY chip on your PCB design.

Note #2:

Decoupling depending on PCB stackups:

Multilayer PCB: Design a PCB stackup with power supply plane and GND plane close together (<0.1 mm or 2 to 3 mils).

This leads to an especially good decoupling at high frequencies (>1 MHz).

Double/single layer PCB: Keep traces of decoupling capacitors to power-supply-pin and ground-pin as short as possible (to keep inductance as low as possible).

EMC Guideline #4 –

Use ground planes on PCB for shielding...

Lower on-board interferences

Use solid filled reference planes (e.g. GND or power supply planes) on a PCB to separate noisy signals (e.g. motor signals) from sensitive signals (e.g. sensor signals).

The reference plane will act as a shield and will lower Electromagnetic Interference (EMI).

Be aware, that the shielding of such a copper plane will primarily be effective for E-fields and not H-field, because copper has a low relative permeability μr and does not shield against (low-frequency) magnetic fields.

Read more about shielding in our Knowledge Database.

EMC Guideline #5 – Route high-frequency signals adjusted to a plane...

Lower radiated emission

This guideline follows out of EMC Guideline #1 and EMC Guideline #2: route high-frequency signals (>50 kHz) ALWAYS closely to an adjusted reference plane (GND or power supply plane, which acts in this case as a high-frequency ground).

For single layer designs: use guard traces close to the high-frequency signal where the return current can flow.

Note #3:

Generally core laminate is more reproducible than pre-preg ("pre-impregnated" composite fibers) regarding thickness and dielectric constant. This means that controlled impedance layers should ideally be routed along the core material, rather than pre-preg.

Read more about PCB layer stackup in our Knowledge Database.

EMC Guideline #6 –

Control rise and fall time...

Lower radiated emission

Lower rise- and fall time of any digital signal (especially clock signals) as far as possible.

Rule Of Thumb #2: Add a series resistor (typically 33 Ohm, close to the driver's output) to all digital signal traces with signal length [inch] higher than rise-/fall-time [nSec].

Rule Of Thumb #3: The approximately highest frequency content in a digital signal depends NOT on the first harmonic (fundamental frequency), it depends on the rise/fall-time:

Where t10%-90% is the rising- or fall-time from 10% to 90% of the slope of a digital signal in [sec] and fknee is the maximum frequency content in [Hz].

Example: Given a digital clock with rise/fall-time of t10%-90%=1.5 nSec which runs over a PCB trace length of 100 mm (3.9 inch).

The highest frequency content in this digital signal is fknee=333MHz and has a wavelength of λ=v/fknee=425mm, where v is the propagation velocity of the electromagnetic energy inside the signal trace on the PCB (typical dielectric constant εr=4.5 for FR-4):

The digital clock signal with a rise/fall-time of 1.5nsec running through a trace on a PCB with FR-4 material results in λ/4=106mm and λ/10=42mm for fmax. 

Given all these facts, the PCB trace of length 100 mm will tend to radiate at high levels (because a trace length or cable of length λ/4 makes a good antenna).

To prevent this: add a series resistor close to the drivers output which will lower the rise/fall-time.

Rule Of Thumb #4:

Every PCB trace of length longer than λ/10 should be considered as a transmission line and no longer as a simple interconnection.

This means that such a trace should be laid out with controlled impedance.

In other words: there should not be any impedance changes / discontinuities along the PCB trace, as these impedance changes / discontinuities lead to e.g. reflections.

Reflections affect the signal integrity (not the topic here) and lead to electromagnetic radiation. 

EMC Guideline #7 –

Add ceramic capacitors close to every pin of a connector...

ESD, lower radiated emission, increase radiated immunity

Filtering of signals directly at the connector is very important! This helps to add Electrostatic Discharge (ESD) immunity to your PCB, lower radiated emission and increase immunity to coupled burst signals on IO cables.

Every signal or power supply line which enters or leaves your PCB needs a ceramic capacitor.

One side of the capacitor close to the connector pin, the other pin tied to the ground plane.

Some Considerations:​

Note #4:

Signals which go outside your device (e.g. a connector which people can touch with their hands), will be tested with an ESD gun (±2kV, ±4kV, ±6kV, ±8kV).

In this case, use capacitors with high voltage rating.

(e.g. >250V, depending on capacitance and ESD test voltage and other components involved, e.g. like ferrite beads between connector pin and capacitor)

EMC Guideline #8 –

Fill top and bottom layers with circuit GND and metalize the PCB edges...

Lower radiated emission

Fill top and bottom layers of a PCB with a solid ground plane around the signals (copper area) and metalize the PCB edges. This helps to minimize radiated emission, because the filled GND areas at top and bottom help to shield inner-layer signals from radiation. Moreover, the filled copper areas help to maintain a low impedance return current path and therefore short current loops.

However, do not forget to place a grid of ground stitch vias throughout the whole PCB (otherwise some small copper islands may radiate), This is very important as i considered it a part of QC...

Take care about the distances between the vias

Plated PCB outside edges (which are connected to circuit GND) help to prevent the inner PCB layers from radiating. Moreover, the plated PCB edges help to increase cooling efficiency of a PCB, because there is an additional copper surface where heat exchange can take place.

The additional costs for metalized PCB edges are low.

EMC Guideline #9 –

Add stitching vias around high-speed signal vias...

Lower radiated emission

This guideline follows directly out of EMC Guideline #2.

Imagine the following scenario: a high-speed signal switches planes on a PCB. In order to minimize ground bounce, you have to minimize the return current path.

There are these two options, depending on the return current path:

1. Identical return current reference nets. In case the two planes have the same reference net with the identical electrical potential (e.g. GND), add two or three stitching vias (between the reference planes) close to high-speed signal via. These stitching vias help to keep current loops as small as possible.

2. Different return current reference reference nets. In case the two reference planes are DC isolated, make sure that the two reference planes are coupled with the lowest impedance possible. This can be achieved with the thinnest possible dielectric layer between them (see the picture below)

EMC Guideline #10 –

Connect circuit GND to chassis at IO area...

Lower radiated emission, conducted immunity, ESD

Do not think this guideline is not important, just because it isn’t listed at first place! This guideline is essential! Bound your circuit GND to chassis at the area where your cable leaves/enters the chassis. Connect it with VERY LOW impedance!

It is important that GND and chassis have the same potential at the IO area:

This prevents radiation, as the GND shows a minimum voltage difference to the chassis (earth).

This helps your IO-signal-filters on your PCB (see EMC Guideline #7) being most effective and keeps ESD pulses away from your circuit. Why? Because incoming noise (burst, ESD) from the cable can directly flow back over chassis to earth.

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LAMBDA INDIA